1/8 april 2001 STW80NF10 n-channel 100v - 0.012 w - 80a to-247 low gate charge stripfet? power mosfet (1) i sd 80a, di/dt 300a/s, v dd v (br)dss , t j t jmax. (2) starting t j = 25c, i d = 80a, v dd = 50v n typical r ds (on) = 0.012 w n exceptional dv/dt capability n 100% avalanche tested n application oriented characterization description this power mosfet series realized with stmicro- electronics unique stripfet process has specifical- ly been designed to minimize input capacitance and gate charge. it is therefore suitable as primary switch in advanced high-efficiency isolated dc-dc converters for telecom and computer application. it is also intended for any application with low gate charge drive requirements. applications n high-efficiency dc-dc converters n ups and motor control absolute maximum ratings ( l ) pulse width limited by safe operating area (*) limited by wire bonding type v dss r ds(on) i d STW80NF10 100 v < 0.015 w 80 a symbol parameter value unit v ds drain-source voltage (v gs = 0) 100 v v dgr drain-gate voltage (r gs = 20 k w ) 100 v v gs gate- source voltage 20 v i d (*) drain current (continuos) at t c = 25c 80 a i d drain current (continuos) at t c = 100c 50 a i dm ( l ) drain current (pulsed) 320 a p tot total dissipation at t c = 25c 300 w derating factor 2 w/c dv/dt (1) peak diode recovery voltage slope 9 v/ns e as (2) single pulse avalanche energy 245 mj t stg storage temperature C65 to 175 c t j max. operating junction temperature 175 c to-247 1 2 3 internal schematic diagram
STW80NF10 2/8 thermal data electrical characteristics (tcase = 25 c unless otherwise specified) off on (1) dynamic rthj-case thermal resistance junction-case max 0.5 c/w rthj-amb thermal resistance junction-ambient max 62.5 c/w t l maximum lead temperature for soldering purpose 300 c symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 100 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating 1a v ds = max rating, t c = 125 c 10 a i gss gate-body leakage current (v ds = 0) v gs = 20v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs , i d = 250a 234v r ds(on) static drain-source on resistance v gs = 10v, i d = 40 a 0.012 0.015 w i d(on) on state drain current v ds > i d(on) x r ds(on)max, v gs =10v 80 a symbol parameter test conditions min. typ. max. unit g fs (1) forward transconductance v ds > i d(on) x r ds(on)max, i d =40 a 20 s c iss input capacitance v ds = 25v, f = 1 mhz, v gs = 0 4300 pf c oss output capacitance 600 pf c rss reverse transfer capacitance 240 pf
3/8 STW80NF10 electrical characteristics (continued) switching on switching off source drain diode note: 1. pulsed: pulse duration = 300 s, duty cycle 1.5 %. 2. pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time v dd = 50v, i d = 40a r g = 4.7 w v gs = 10v (see test circuit, figure 3) 40 ns t r rise time 145 ns q g total gate charge v dd = 80v, i d = 80a, v gs = 10v 140 189 nc q gs gate-source charge 23 nc q gd gate-drain charge 51 nc symbol parameter test conditions min. typ. max. unit t d(off) turn-off-delay time v dd = 27v, i d = 40a, r g =4.7 w, v gs = 10v (see test circuit, figure 3) 134 ns t f fall time 115 ns t d(off) off-voltage rise time vclamp =80v, i d =80a r g =4.7 w, v gs = 10v 111 ns t f fall time (see test circuit, figure 5) 125 ns t c cross-over time 185 ns symbol parameter test conditions min. typ. max. unit i sd source-drain current 80 a i sdm (1) source-drain current (pulsed) 320 a v sd (2) forward on voltage i sd = 80a, v gs = 0 1.5 v t rr reverse recovery time i sd = 80a, di/dt = 100a/s, v dd = 50v, t j = 150c (see test circuit, figure 5) 155 ns q rr reverse recovery charge 850 nc i rrm reverse recovery current 11 a thermal impedence safe operating area
STW80NF10 4/8 output characteristics capacitance variations gate charge vs gate-source voltage transconductance static drain-source on resistance transfer characteristics
5/8 STW80NF10 normalized on resistance vs temperature normalized gate thereshold voltage vs temp. source-drain diode forward characteristics
STW80NF10 6/8 fig. 5: test circuit for inductive load switching and diode recovery times fig. 4: gate charge test circuit fig. 2: unclamped inductive waveform fig. 1: unclamped inductive load test circuit fig. 3: switching times test circuit for resistive load
7/8 STW80NF10 dim. mm inch min. typ. max. min. typ. max. a 4.7 5.3 0.185 0.209 d 2.2 2.6 0.087 0.102 e 0.4 0.8 0.016 0.031 f 1 1.4 0.039 0.055 f3 2 2.4 0.079 0.094 f4 3 3.4 0.118 0.134 g 10.9 0.429 h 15.3 15.9 0.602 0.626 l 19.7 20.3 0.776 0.779 l3 14.2 14.8 0.559 0.582 l4 34.6 1.362 l5 5.5 0.217 m 2 3 0.079 0.118 p025p to-247 mechanical data
STW80NF10 8/8 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectroni cs. specifi cation mentio ned in this publication are subject to change without notice. this publication supersedes and replaces all in formation previou sly supplied. stmicroel ectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectron ics. the st logo is a trademark of stmicroelectronics ? 2001 stmicroelectronics C pr inted in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malay sia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com
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